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MT93L00A Multi-Channel Voice Echo Canceller
Data Sheet
Not recommended for new designs. Use the ZL38065, 32 channel VEC with enhanced algorithm.
March 2005
Ordering Information MT93L00AB MT93L00AV 100-Pin LQFP 208-Ball LBGA
Features
* Independent multiple channels of echo cancellation; from 32 channels of 64 ms to 16 channels of 128 ms with the ability to mix channels at 128 ms or 64 ms in any combination Independent Power Down mode for each group of 2 channels for power management ITU-T G.165 and G.168 compliant Field proven, high quality performance Compatible to ST-BUS and GCI interface at 2 Mbps serial PCM PCM coding, /A-Law ITU-T G.711 or sign magnitude Per channel Fax/Modem G.164 2100 Hz or G.165 2100 Hz phase reversal Tone Disable Per channel echo canceller parameters control Transparent data transfer and mute Fast reconvergence on echo path changes Non-Linear Processor with high quality subjective performance
-40C to +85C * * * * * * * * * * * * * * Protection against narrow band signal divergence Offset nulling of all PCM channels 10 MHz or 20 MHz master clock operation 3.3 V pads and 1.8 V Logic core operation with 5 V tolerant inputs No external memory required Non-multiplexed microprocessor interface IEEE-1149.1 (JTAG) Test Access Port Applications Voice over IP network gateways Voice over ATM, Frame Relay T1/E1/J1 multichannel echo cancellation Wireless base stations Echo Canceller pools DCME, satellite and multiplexer systems
VDD2 (1.8 V)
* * * * * * * * * *
VDD1 (3.3 V)
VSS
ODE
Echo Canceller Pool
Rin Sin MCLK Fsel PLL Serial to Parallel
Group 0
ECA/ECB
Group 1
ECA/ECB
Group 2
ECA/ECB
Group 3
ECA/ECB
Parallel to Serial
Rout Sout
Group 4
ECA/ECB
Group 5
ECA/ECB
Group 6
ECA/ECB
Group 7
ECA/ECB
Group 8
ECA/ECB
Group 9
ECA/ECB
Group 10
ECA/ECB
Group 11
ECA/ECB
Group 12
ECA/ECB C4i F0i Timing Unit
Group 13
ECA/ECB
Group 14
ECA/ECB
Group 15
ECA/ECB
Note: Refer to Figure 4 for Echo Canceller block diagram
IC0
RESET Microprocessor Interface Test Port
DS CS R/W A10-A0 DTA
D7-D0
IRQ TMS TDI TDO TCK TRST
Figure 1 - Functional Block Diagram 1
Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2002-2005, Zarlink Semiconductor Inc. All Rights Reserved.
MT93L00A
Description
Data Sheet
The MT93L00 Voice Echo Canceller implements a cost effective solution for telephony voice-band echo cancellation conforming to ITU-T G.168 requirements. The MT93L00 architecture contains 16 groups of two echo cancellers (ECA and ECB) which can be configured to provide two channels of 64 milliseconds or one channel of 128 milliseconds echo cancellation. This provides 32 channels of 64 milliseconds to 16 channels of 128 milliseconds echo cancellation or any combination of the two configurations. The MT93L00 supports ITU-T G.165 and G.164 tone disable requirements.
PLLVSS1
PLLVSS2
PLLVDD
VDD1
VDD2
mclk NC
IC0 IC0 IC0
IC0
IC0
VDD1
77
VSS
fsel
NC
NC
NC
NC
NC
VSS
NC
NC
NC
78
TMS TDI TDO TCK VSS TRSTB IC0 RESETB IRQB DS CS R/W DTA VDD2 D0 D1 D2 VSS D3 D4 D5 D6 D7 NC NC
NC
76
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
NC NC NC IC0 IC0 IC0 VSS IC0 IC0 IC0 IC0 VDD2 C4ib Foib Rin Sin Rout Sout ODE VSS NC NC NC NC NC
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52
A7
A8
A9
VDD2
A10
NC VDD1
NC
VSS
VDD1
IC0 VSS
IC0
NC NC
NC
Figure 2 - 100 Pin LQFP
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Zarlink Semiconductor Inc.
NC
A6
NC
A0
A1
A2
A3
A4
A5
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29
MT93L00AB (100 pin LQFP)
VDD1 = 3.3 V
VDD2 = 1.8 V
51
30
31
50
32
33
34
35
36
37
38
39
41 40
42
43
45 44
46
47
48
49
MT93L00A
1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Data Sheet
16
A
VSS ICO ICO NC NC NC NC NC NC NC NC TDI
ICO VSS ICO
VSS ICO VSS
c4i VDD1 VDD1 VSS VSS VDD1 VSS
VDD1 F0i VSS VDD1
ICO VSS VDD2
VSS Rin VSS
Sout VSS VDD1 VSS
VDD1 Rout VSS VDD1
ICO VDD1 VDD1 VSS
VSS Sin VSS VDD1
ICO VSS VSS VSS
VSS ODE VSS VSS VDD1
NC VSS VSS VDD1 VSS VDD1
VSS VSS NC NC ICO ICO NC NC NC NC NC VSS
VSS VSS VSS A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 VSS VSS
B
C
D
ICO VDD1 ICO NC MCLK Fsel VSS VDD1 VSS
VDD2 VDD1
E
F
MT93L00AV
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
VSS
G
VDD2 VDD2 VSS VDD1 VSS VDD1 VSS VSS VDD1 VSS VDD1 VSS
H
VDD1 VDD1 VDD2 VDD2
J
ICO
K
ICO PLLVSS PLLVDD NC TMS VSS VSS
L
M
VDD1 VDD1 VSS VSS VSS VDD1 VSS VSS VDD1 VDD1 VDD1 D2 VSS VSS DTA VSS VDD1 VDD1 VDD1 D3 VSS VSS IRQ D4 VDD1 VDD1 VDD1 VSS VSS VSS DS D5 VDD2 VDD2 VDD1 VDD1
TDO TRST
N
VSS VSS CS D6
VDD1 VDD1 VSS VSS VSS VDD1 VSS D7
TCK
P R T
VSS VSS D0
ICO VSS
RESET V R/W DD1 VSS D1 VDD1
1
- A1 corner is identified by metallized markings.
Figure 3 - 208 Ball LBGA
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Zarlink Semiconductor Inc.
MT93L00A
Pin Description PIN # 208-Ball LBGA 100 PIN LQFP PIN Name VSS Ground.
Data Sheet
Description
A1,A3,A7,A11,A13,A15, 5, 18, 32, A16,B2,B6,B8,B12, 42, 56, 69, B14,B15,B16,C3,C5,C7, 81, 98 C9,C11,C12,C13,C14, C16, D4,D8,D10,D12,D13,E3, E4,E14,F13,G3,G4,G7,G8, G9,G10,H7,H8,H9, H10,H13,H14,J7,J8,J9, J10,K7,K8,K9,K10,K13, K14,L3,L4,M13,M14,M15, N3,N4,N5,N7,N9,N11,N13, P2,P3,P5,P7,P9.P11,P13, P14,R2,R14,R15,R16,T1, T3,T7,T10, T14,T16 A5,A9,B4,B10,C4,C8,C10, D3,D5,D7,D9,D11,D14,E1 3, F3,F4,F14,H3,H4,J13,J14, L13,L14,M3,M4,N6,N8, N10,N14,N15,P4,P6,P8, P10,P15,R4,R6,R8,R10, R12,T5,T12 27, 48, 77, 100
VDD1
Positive Power Supply. Nominally 3.3 V
C6,D6,J3,J4,N12,P12, G13,G14
14, 37, 64, 91
VDD2
These pins should be wired to Vdd2= 1.8 V.
E15,F15,A12,A10,A6,A2, 7,41,43,65,6 B1,B3,C1,C2,D2,E2,J2,K2, 6,67,68,70, R1 71,72,86,87, 88,93,94 A14,C15,D1,D15,E1,F1, G1, G15,H1,H15,J1,J15,K1, K15,L1,L15,F2,L2 24,25,26,44, 45,46,47,49, 51,52,53,54, 55,73,74,75, 76,78,79,80, 82,83,84,85, 89,99
IC0
Internal Connection. These pins must be connected to VSS for normal operation.
NC
No connection. These pins must be left open for normal operation.
R9
9
IRQ
Interrupt Request (Open Drain Output). This output goes low
when an interrupt occurs in any channel. IRQ returns high when all the interrupts have been read from the Interrupt FIFO Register. A pull-up resistor (1 K typical) is required at this output.
R11 R13 R5
10 11 12
DS CS R/W
Data Strobe (Input). This active low input works in conjunction with CS to enable the read and write operations. Chip Select (Input). This active low input is used by a microprocessor to activate the microprocessor port. Read/Write (Input). This input controls the direction of the data bus lines (D7-D0) during a microprocessor access.
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Zarlink Semiconductor Inc.
MT93L00A
Pin Description (continued) PIN # 208-Ball LBGA R7 100 PIN LQFP 13 PIN Name DTA
Data Sheet
Description Data Transfer Acknowledgment (Open Drain Output). This active low output indicates that a data bus transfer is completed. A pull-up resistor (1 K typical) is required at this output.
T2,T4,T6,T8,T9,T11, T13,T15
P16,N16,M16,L16,K16, J16,H16,G16,F16,E16, D16
15,16,17, 19,20,21, 22,23
D0 - D3, Data Bus D0 - D7 (Bidirectional). These pins form the 8-bit D4 - D7 bidirectional data bus of the microprocessor port.
28,29,30,31, A0 - A10 Address A0 to A10 (Input). These inputs provide the A10 - A0 33,34,35,36, address lines to the internal registers. 38,39,40 57
B13
ODE
Output Drive Enable (Input). This input pin is logically AND'd with the ODE bit-6 of the Main Control Register. When both ODE bit and ODE input pin are high, the Rout and Sout ST-BUS outputs are enabled. When the ODE bit is low or the ODE input pin is low, the Rout and Sout ST-BUS outputs are high impedance. Send PCM Signal Output (Output). Port 1 TDM data output streams. Sout pin outputs serial TDM data streams at 2.048 Mbps with 32 channels per stream. Receive PCM Signal Output (Output). Port 2 TDM data output streams. Rout pin outputs serial TDM data streams at 2.048 Mbps with 32 channels per stream. Send PCM Signal Input (Input). Port 2 TDM data input streams. Sin pin receives serial TDM data streams at 2.048 Mbps with 32 channels per stream. Receive PCM Signal Input (Input). Port 1 TDM data input streams. Rin pin receives serial TDM data streams at 2.048 Mbps with 32 channels per stream. Frame Pulse (Input). This input accepts and automatically identifies frame synchronization signals formatted according to ST-BUS or GCI interface specifications. Serial Clock (Input). 4.096 MHz serial clock for shifting data in/out on the serial streams (Rin, Sin, Rout, Sout). Master Clock (Input). Nominal 10 MHz or 20 MHz Master Clock input. May be connected to an asynchronous (relative to frame signal) clock source. Frequency select (Input). This input selects the Master Clock frequency operation. When Fsel pin is low, nominal 19.2 MHz Master Clock input must be applied. When Fsel pin is high, nominal 9.6 MHz Master Clock input must be applied.
A8
58
Sout
B9
59
Rout
B11
60
Sin
B7
61
Rin
B5
62
F0i
A4 G2
63 90
C4i MCLK
H2
92
Fsel
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Zarlink Semiconductor Inc.
MT93L00A
Pin Description (continued) PIN # 208-Ball LBGA K3 K4 M2 100 PIN LQFP 95,97 96 1 PIN Name
Data Sheet
Description
PLLVss1 PLL Ground. Must be connected to VSS. PLLVss2 PLLVDD PLL Power Supply. Must be connected to VDD2. TMS Test Mode Select (3.3 V Input). JTAG signal that controls the state transitions of the TAP controller. This pin is pulled high by an internal pull-up when not driven. Test Serial Data In (3.3 V Input). JTAG serial test instructions and data are shifted in on this pin. This pin is pulled high by an internal pull-up when not driven. Test Serial Data Out (Output). JTAG serial data is output on this pin on the falling edge of TCK. This pin is held in high impedance state when JTAG scan is not enabled. Test Clock (3.3 V Input). Provides the clock to the JTAG test logic. Test Reset (3.3 V Input). Asynchronously initializes the JTAG TAP controller by putting it in the Test-Logic-Reset state. This pin should be pulsed low on power-up or held low, to ensure that the MT93L00 is in the normal functional mode. This pin is pulled by an internal pull-down when not driven.
M1
2
TDI
N1
3
TDO
P1 N2
4 6
TCK TRST
R3
8
RESET Device Reset (Schmitt Trigger Input). An active low resets the device and puts the MT93L00 into a low-power stand-by mode. When the RESET pin is returned to logic high and a clock is applied to the MCLK pin, the device will automatically execute initialization routines, which preset all the Control and Status Registers to their default power-up values.
Device Overview
The MT93L00 architecture contains 32 echo cancellers divided into 16 groups. Each group has two echo cancellers, Echo Canceller A and Echo Canceller B. Each group can be configured in Normal, Extended Delay or Back-to-Back configurations. In Normal configuration, a group of echo cancellers provides two channels of 64 ms echo cancellation, which run independently on different channels. In Extended Delay configuration, a group of echo cancellers achieves 128 ms of echo cancellation by cascading the two echo cancellers (A & B). In Back-toBack configuration, the two echo cancellers from the same group are positioned to cancel echo coming from both directions in a single channel, providing full-duplex 64 ms echo cancellation. Each echo canceller contains the following main elements (see Figure 4). * * * * * * Adaptive Filter for estimating the echo channel Subtractor for cancelling the echo Double-Talk detector for disabling the filter adaptation during periods of double-talk Path Change detector for fast reconvergence on major echo path changes Instability Detector to combat oscillation in very low ERL environments Non-Linear Processor for suppression of residual echo
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Zarlink Semiconductor Inc.
MT93L00A
* * * * * * Disable Tone Detectors for detecting valid disable tones at send and receive path inputs Narrow-Band Detector for preventing Adaptive Filter divergence from narrow-band signals Offset Null filters for removing the DC component in PCM channels 12 dB attenuator for signal attenuation Parallel controller interface compatible with Motorola microcontrollers PCM encoder/decoder compatible with /A-Law ITU-T G.711 or Sign-Magnitude coding
Data Sheet
Each echo canceller in the MT93L00 has four functional states: Mute, Bypass, Disable Adaptation and Enable Adaptation. These are explained in the section entitled Echo Canceller Functional States.
Sin (channel N)
/A-Law/ Linear
Offset Null
+
Adaptive Filter
Non-Linear Processor
Linear/ /A-Law MuteS Path Change Detector Disable Tone Detector /A-Law/ Linear
Sout (channel N)
Control
Disable Tone Detector ST-BUS PORT2
Programmable Bypass
Microprocessor Interface Double-Talk Detector MuteR Offset Null
ST-BUS PORT1
Instability Detector Rout (channel N) Linear/ /A-Law
Narrow-Band Detector 12 dB Attenuator
Rin (channel N)
Echo Canceller (N), where 0 N 31
Figure 4 - Echo Canceller Functional Block Diagram Adaptive Filter The adaptive filter adapts to the echo path and generates an estimate of the echo signal. This echo estimate is then subtracted from Sin. For each group of echo cancellers, the adaptive filter is a 1024 tap FIR adaptive filter which is divided into two sections. Each section contains 512 taps providing 64 ms of echo estimation. In Normal configuration, the first section is dedicated to channel A and the second section to channel B. In Extended Delay configuration, both sections are cascaded to provide 128 ms of echo estimation in channel A. In Back-to Back configuration, the first section is used in the receive direction and the second section is used in the transmit direction for the same channel.
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Zarlink Semiconductor Inc.
MT93L00A
Double-Talk Detector
Data Sheet
Double-Talk is defined as those periods of time when signal energy is present in both directions simultaneously. When this happens, it is necessary to disable the filter adaptation to prevent divergence of the Adaptive Filter coefficients. Note that when double-talk is detected, the adaptation process is halted but the echo canceller continues to cancel echo using the previous converged echo profile. A double-talk condition exists whenever the relative signal levels of Rin (Lrin) and Sin (Lsin) meet the following condition:
Lsin > Lrin + 20log10(DTDT)
where DTDT is the Double-Talk Detection Threshold. Lsin and Lrin are signal levels expressed in dBm0. A different method is used when it is uncertain whether Sin consists of a low level double-talk signal or an echo return. During these periods, the adaptation process is slowed down but it is not halted. In G.168 standard, the echo return loss is expected to be at least 6 dB. This implies that the Double-Talk Detector Threshold (DTDT) should be set to 0.5 (-6 dB). However, in order to get additional guardband, the DTDT is set internally to 0.5625 (-5 dB). In some applications the return loss can be higher or lower than 6 dB. The MT93L00 allows the user to change the detection threshold to suit each application's need. This threshold can be set by writing the desired threshold value into the DTDT register. The DTDT register is 16 bits wide. The register value in hexadecimal can be calculated with the following equation:
DTDT(hex) = hex(DTDT(dec) * 32768)
where 0 < DTDT(dec) < 1 Example: For DTDT = 0.5625 (-5 dB), the hexadecimal value becomes hex(0.5625 * 32768) = 4800h Path Change Detector Integrated into the MT93L00A is a Path Change Detector. This permits fast reconvergence when a major change occurs in the echo channel. Subtle changes in the echo channel are also tracked automatically once convergence is achieved, but at a much slower speed. The Path Change Detector is activated by setting the PathDet bit in Control Register A3/B3 to "1". An optional path clearing feature can be enabled by setting the PathClr bit in Control Register A3/B3 to "1". With path clearing turned on, the existing echo channel estimate will also be cleared (i.e. the adaptive filter will be filled with zeroes) upon detection of a major path change.
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Zarlink Semiconductor Inc.
MT93L00A
Non-Linear Processor (NLP)
Data Sheet
After echo cancellation, there is always a small amount of residual echo which may still be audible. The MT93L00 uses an NLP to remove residual echo signals which have a level lower than the Adaptive Suppression Threshold (TSUP in G.168). This threshold depends upon the level of the Rin (Lrin) reference signal as well as the programmed value of the Non-Linear Processor Threshold register (NLPTHR). TSUP can be calculated by the following equation:
TSUP = Lrin + 20log10(NLPTHR)
where NLPTHR is the Non-Linear Processor Threshold register value and Lrin is the relative power level expressed in dBm0. When the level of residual error signal falls below TSUP, the NLP is activated further attenuating the residual signal by an additional 36 dB. To prevent a perceived decrease in background noise due to the activation of the NLP, a spectrally-shaped comfort noise, equivalent in power level to the background noise, is injected. This keeps the perceived noise level constant. Consequently, the user does not hear the activation and de-activation of the NLP. The NLP processor can be disabled by setting the NLPDis bit to "1" in Control Register 2. The NLPTHR register is 16 bits wide. The register value in hexadecimal can be calculated with the following equation:
NLPTHR(hex) = hex(NLPTHR(dec) * 32768)
where 0 < NLPTHR(dec) < 1 The comfort noise injector can be disabled by setting the INJDis bit to "1" in Control Register A1/B1. It should be noted that the NLPTHR is valid and the comfort noise injection is active only when the NLP is enabled. If the comfort noise injector is unable to correctly match the level of the background noise (because of peculiar spectral characteristics, for example), the injected level can be fine-tuned using the Noise Scaling register. A neutral value of 80(hex) will prevent any scaling. Values less than 80(hex) will reduce the noise level, values greater than 80(hex) will increase the noise level. The scaling is done linearly. Example: To decrease the comfort noise level by 3 dB, the register value would be 10 ^ (-3 / 20) * 128 = 0.71 * 128 = 91(dec) = 5B(hex) The default factory setting for the Noise Scaling register should be adequate for most operating environments. It is unlikely that it will need to be changed. It has also been set to a value which will ensure G.168 compliance. Disable Tone Detector G.165 recommendation defines the disable tone as having the following characteristics: 2100 Hz (21 Hz) sine wave, a power level between -6 to -31 dBm0, and a phase reversal of 180 degrees ( 25 degrees) every 450 ms ( 25 ms). If the disable tone is present for a minimum of one second with at least one phase reversal, the Tone Detector will trigger.
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Zarlink Semiconductor Inc.
MT93L00A
Data Sheet
G.164 recommendation defines the disable tone as a 2100 Hz (21 Hz) sine wave with a power level between 0 to -31 dBm0. If the disable tone is present for a minimum of 400 milliseconds, with or without phase reversal, the Tone Detector will trigger. The MT93L00 has two Tone Detectors per channels (for a total of 64) in order to monitor the occurrence of a valid disable tone on both Rin and Sin. Upon detection of a disable tone, TD bit of the Status Register will indicate logic high and an interrupt is generated (i.e. IRQ pin low). Refer to Figure 5 and to the Interrupts section.
Rin Sin
Tone Tone
Detector Detector Echo Canceller A
ECA Status reg TD bit
Rin Sin
Tone Tone
Detector Detector Echo Canceller B
ECB Status reg TD bit
Figure 5 - Disable Tone Detection Once a Tone Detector has been triggered, there is no longer a need for a valid disable tone (G.164 or G.165) to maintain Tone Detector status (i.e. TD bit high). The Tone Detector status will only release (i.e. TD bit low) if the signals Rin and Sin fall below -30 dBm0, in the frequency range of 390 Hz to 700 Hz, and below -34 dBm0, in the frequency range of 700 Hz to 3400 Hz, for at least 400 ms. Whenever a Tone Detector releases, an interrupt is generated (i.e. IRQ pin low). The selection between G.165 and G.164 tone disable is controlled by the PHDis bit in Control Register 2 on a per channel basis. When the PHDis bit is set to 1, G.164 tone disable requirements are selected. In response to a valid disable tone, the echo canceller must be switched from the Enable Adaptation state to the Bypass state. This can be done in two ways, automatically or externally. In automatic mode, the Tone Detectors internally control the switching between Enable Adaptation and Bypass states. The automatic mode is activated by setting the AutoTD bit in Control Register 2 to high. In external mode, an external controller is needed to service the interrupts and poll the TD bits in the Status Registers. Following the detection of a disable tone (TD bit high) on a given channel, the external controller must switch the echo canceller from Enable Adaptation to Bypass state. Instability Detector In systems with very low echo channel return loss (ERL), there may be enough feedback in the loop to cause stability problems in the adaptive filter. This instability can result in variable pitched ringing or oscillation. Should this ringing occur, the Instability Detector will activate and suppress the oscillations. The Instability Detector is activated by setting the RingClr bit in Control Register A3/B3 to "1". Narrow Band Signal Detector (NBSD) Single or dual frequency tones (i.e. DTMF tones) present in the receive input (Rin) of the echo canceller for a prolonged period of time may cause the Adaptive Filter to diverge. The Narrow Band Signal Detector (NBSD) is designed to prevent this by detecting single or dual tones of arbitrary frequency, phase, and amplitude. When narrow band signals are detected, adaptation is halted but the echo canceller continues to cancel echo. The NBSD can be disabled by setting the NBDis bit to "1" in Control Register 2.
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Zarlink Semiconductor Inc.
MT93L00A
Offset Null Filter
Data Sheet
Adaptive filters in general do not operate properly when a DC offset is present at any inputs. To remove the DC component, the MT93L00 incorporates Offset Null filters in both Rin and Sin inputs. The offset null filters can be disabled by setting the HPFDis bit to "1" in Control Register 2. ITU-T G.168 Compliance The MT93L00 has been certified G.168 compliant in all 64 ms cancellation modes (i.e. Normal and Back-to-Back configurations) by in-house testing with the DSPG ECT-1 echo canceller tester. It should be noted that G.168 compliance is not claimed for the 128 ms Extended Delay mode, although subjectively no difference can be noticed.
Device Configuration
The MT93L00 architecture contains 32 echo cancellers divided into 16 groups. Each group has two echo cancellers which can be individually controlled (Echo Canceller A and B). They can be set in three distinct configurations: Normal, Back-to-Back, and Extended Delay. See Figure 6. Normal Configuration In Normal configuration, the two echo cancellers (Echo Canceller A and B) are positioned in parallel, as shown in Figure 6a, providing 64 milliseconds of echo cancellation in two channels simultaneously. Back-to-Back Configuration In Back-to-Back configuration, the two echo cancellers from the same group are positioned to cancel echo coming from both directions in a single channel providing full-duplex 64 ms echo cancellation. See Figure 6c. This configuration uses only one timeslot on PORT1 and PORT2 and the second timeslot normally associated with ECB contains undefined data. Back-to-Back configuration allows a no-glue interface for applications where bidirectional echo cancellation is required. Back-to-Back configuration is selected by writing "1" into the BBM bit of both Control Register A1 and Control Register B1 of a given group of echo cancellers. Table 2 shows the 16 groups of 2 cancellers that can be configured into Back-to-Back. Examples of Back-to-Back configuration include positioning one group of echo cancellers between a CODEC and a transmission device or between two codecs for echo control on analog trunks. Extended Delay configuration In this configuration, the two echo cancellers from the same group are internally cascaded into one 128 milliseconds echo canceller. See Figure 6b. This configuration uses only one timeslot on PORT1 and PORT2 and the second timeslot normally associated with ECB contains undefined data. Extended Delay configuration is selected by writing "1" into the ExtDl bit in Echo Canceller A, Control Register A1. For a given group, only Echo Canceller A, Control Register A1, has the ExtDl bit. Control Register B1, bit-0 must always be set to zero. Table 2 shows the 16 groups of 2 cancellers that can each be configured into 64 ms or 128 ms echo tail capacity.
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Zarlink Semiconductor Inc.
MT93L00A
Echo Canceller Functional States
Data Sheet
Each echo canceller has four functional states: Mute, Bypass, Disable Adaptation and Enable Adaptation. Mute In Normal and in Extended Delay configurations, writing a "1" into the MuteR bit replaces Rin with quiet code which is applied to both the Adaptive Filter and Rout. Writing a "1" into the MuteS bit replaces the Sout PCM data with quiet code.
SIGN/ MAGNITUDE A-Law 80h CCITT (G.711)
LINEAR 16 bits 2's complement +Zero (quiet code) 0000h
-Law
-Law
FFh
A-Law D5h
Table 1 - Quiet PCM Code Assignment In Back-to-Back configuration, writing a "1" into the MuteR bit of Echo Canceller A, Control Register 2, causes quiet code to be transmitted on Rout. Writing a "1" into the MuteS bit of Echo Canceller A, Control Register 2, causes quiet code to be transmitted on Sout. In Extended Delay and in Back -to -Back configurations, MuteR and MuteS bits of Echo Canceller B must always be "0". Refer to Figure 4 and to Control Register 2 for bit description. Bypass The Bypass state directly transfers PCM codes from Rin to Rout and from Sin to Sout. When Bypass state is selected, the Adaptive Filter coefficients are reset to zero. Bypass state must be selected for at least one frame (125 s) in order to properly clear the filter.
Sin echo path A
channel A -
+
Sout
Sin echo path A
channel A -
+
Sout
Adaptive Filter (64 ms) channel A Rin E.C.A channel B Optional -12dB pad
Adaptive Filter (128 ms) channel A
Optional -12dB pad
Rout PORT2
Rout PORT2
Rin PORT1
PORT1
E.C.A
b) Extended Delay Configuration (128 ms)
+ Sin echo path +
Optional -12dB pad
Sout Adaptive Filter (64 ms) echo path
echo path B channel B
Adaptive Filter (64 ms)
Adaptive Filter (64 ms)
E.C.B
Optional -12dB pad
Rout PORT2 E.C.A
Optional -12dB pad
+ E.C.B
Rin PORT1
a) Normal Configuration (64 ms)
c) Back-to-Back Configuration (64 ms)
Figure 6 - Device Configuration
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Zarlink Semiconductor Inc.
MT93L00A
Disable Adaptation
Data Sheet
When the Disable Adaptation state is selected, the Adaptive Filter coefficients are frozen at their current value. The adaptation process is halted, however, the echo canceller continues to cancel echo. Enable Adaptation In Enable Adaptation state, the Adaptive Filter coefficients are continually updated. This allows the echo canceller to model the echo return path characteristics in order to cancel echo. This is the normal operating state. The echo canceller functions are selected in Control Register A1/B1 and Control Register 2 through four control bits: MuteS, MuteR, Bypass and AdaptDis. Refer to the Registers Description for details.
125 sec
F0i ST-Bus F0i GCI interface
Rin/Sin Rout/Sout
Channel 0
Channel 1
Channel 30
Channel 31
Note: Refer to Figures 11 and 12 for timing details
Figure 7 - ST-BUS and GCI Interface Channel Assignment for 2 Mbps Data Streams
MT93L00 Throughput Delay
The throughput delay of the MT93L00 varies according to the device configuration. For all device configurations, Rin to Rout has a delay of two frames and Sin to Sout has a delay of three frames. In Bypass state, the Rin to Rout and Sin to Sout paths have a delay of two frames.
Serial PCM I/O channels
There are two sets of TDM I/O streams, each with channels numbered from 0 to 31. One set of input streams is for Receive (Rin) channels, and the other set of input streams is for Send (Sin) channels. Likewise, one set of output streams is for Rout pcm channels, and the other set is for Sout channels. See Figure 7 for channel allocation. The arrangement and connection of PCM channels to each echo canceller is a two port I/O configuration for each set of PCM Send and Receive channels, as illustrated in Figure 4. Serial Data Interface Timing The MT93L00 provides ST-BUS and GCI interface timing. The Serial Interface clock frequency, C4i, is 4.096 MHz. The input and output data rate of the ST-Bus and GCI bus is 2.048 Mbps. The 8 KHz input frame pulse can be in either ST-BUS or GCI format. The MT93L00 automatically detects the presence of an input frame pulse and identifies it as either ST-BUS or GCI. In ST-BUS format, every second falling edge of the C4i clock marks a bit boundary, and the data is clocked in on the rising edge of C4i, three quarters of the way into the bit cell (See Figure 11). In GCI format, every second rising edge of the C4i clock marks the bit boundary, and data is clocked in on the second falling edge of C4i, half the way into the bit cell (see Figure 12).
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Zarlink Semiconductor Inc.
MT93L00A
Base Addr + Echo Canceller A 00h Control Reg A1 01h Control Reg 2 02h Status Reg 03h Reserved 04h Flat Delay Reg 05h Reserved 06h Decay Step Size Reg 07h Decay Step Number 08h Control Reg A3 09h Control Reg A4 0Ah Noise Scaling 0Bh Injection Rate 0Ch Rin Peak Detect Reg 0Eh Sin Peak Detect Reg 10h Error Peak Detect Reg 12h Reserved 14h DTDT Reg 16h Reserved 18h NLPTHR 1Ah Step Size, MU 1Ch Reserved 1Eh Reserved Base Addr + Echo Canceller B 20h Control Reg B1 21h Control Reg 2 22h Status Reg 23h Reserved 24h Flat Delay Reg 25h Reserved 26h Decay Step Size Reg 27h Decay Step Number 28h Control Reg B3 29h Control Reg B4 2Ah Noise Scaling 2Bh Injection Rate 2Ch Rin Peak Detect Reg 2Eh Sin Peak Detect Reg 30h Error Peak Detect Reg 32h Reserved 34h DTDT Reg 36h Reserved 38h NLPTHR 3Ah Step Size, MU 3Ch Reserved 3Eh Reserved
Data Sheet
Figure 8 - Memory Mapping of Per Channel Control and Status Registers
Memory Mapped Control and Status Registers
Internal memory and registers are memory mapped into the address space of the HOST interface. The internal dual ported memory is mapped into segments on a "per channel" basis to monitor and control each individual echo canceller and associated PCM channels. For example, in Normal configuration, echo canceller #5 makes use of Echo Canceller B from group 2. It occupies the internal address space from 0A0h to 0BFh and interfaces to PCM channel #5 on all serial PCM I/O streams. As illustrated in Figure 8, the "per channel" registers provide independent control and status bits for each echo canceller. Figure 9 shows the memory map of the control/status register blocks for all echo cancellers. When Extended Delay or Back-to-Back configuration is selected, Control Register A1/B1 and Control Register 2 of the selected group of echo cancellers require special care. Refer to the Register description section.
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Zarlink Semiconductor Inc.
MT93L00A
Data Sheet
Table 2 is a list of the channels used for the 16 groups of echo cancellers when they are configured as Extended Delay or Back-to-Back. Normal Configuration For a given group (group 0 to 15), 2 PCM I/O channels are used. For example, group 1 Echo Cancellers A and B, channels 2 and 3 are active. Group 0 1 2 3 4 5 6 7 Channel 0, 1 2, 3 4, 5 6, 7 8, 9 10, 11 12, 13 14, 15 Group 8 9 10 11 12 13 14 15 Channel 16, 17 18, 19 20, 21 22, 23 24, 25 26, 27 28, 29 30, 31
Table 2 - Group and Channel Allocation Extended Delay Configuration For a given group (group 0 to 15), only one PCM I/O channel is active (Echo Canceller A) and the other channel carries don't care data. For example, group 2, Echo Canceller A (Channel 4) will be active and Echo Canceller B (Channel 5) will carry don't care data. Back-to-Back Configuration For a given group (group 0 to 15), only one PCM I/O channel is active (Echo Canceller A) and the other channel carries don't care data. For example, group 5, Echo Canceller A (Channel 10) will be active and Echo Canceller B (Channel 11) will carry don't care data.
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Zarlink Semiconductor Inc.
MT93L00A
Channel 0, EC A Ctrl/Stat Registers Channel 1, EC B Ctrl/Stat Registers 0000h --> 001Fh 0020h --> 003Fh
Data Sheet
Group 0 Echo Cancellers Registers Group 1 Echo Cancellers Registers
Channel 2, EC A Ctrl/Stat Registers Channel 3, EC B Ctrl/Stat Registers
0040h --> 005Fh 0060h --> 007Fh
Groups 2 --> 14 Echo Cancellers Registers
Group 15 Echo Cancellers Registers
Channel 30, EC A Ctrl/Stat Registers Channel 31, EC B Ctrl/Stat Registers
03C0h --> 03DFh 03E0h --> 03FFh
Main Control Registers <15:0> Interrupt FIFO Register Test Register
0400h --> 040Fh 0410h 0411h
Figure 9 - Memory Mapping
Power Up Sequence
On power up, the RESET pin must be held low for 100s. Forcing the RESET pin low will put the MT93L00 in power down state. In this state, all internal clocks are halted, D<7:0>, Sout, Rout, DTA and IRQ pins are tristated. The 16 Main Control Registers, the Interrupt FIFO Register and the Test Register are reset to zero. When the RESET pin returns to logic high and a valid MCLK is applied, the user must wait 500 s for the PLL to lock. C4i and F0i can be active during this period. At this point, the echo canceller must have the internal registers reset to an initial state. This is accomplished by one of two methods. The user can either issue a second hardware reset or perform a software reset. A second hardware reset is performed by driving the RESET pin low for at least 500 ns and no more than 1500 ns before being released. A software reset is accomplished by programming a "1" to each of the PWUP bits in the Main Control Registers, waiting 250 s (2 frames) and then programming a "0" to each of the PWUP bits. The user must then wait 500 s for the PLL to relock. Once the PLL has locked, the user can power up the 16 groups of echo cancellers individually by writing a "1" into the PWUP bit in Main Control Register of each echo canceller group. For each group of echo cancellers, when the PWUP bit toggles from zero to one, echo cancellers A and B execute their initialization routine. The initialization routine sets their registers, Base Address+00H to Base Address+3FH, to the default Reset Value and clears the Adaptive Filter coefficients. Two frames are necessary for the initialization routine to execute properly. Once the initialization routine is executed, the user can set the per channel Control Registers, Base Address+00H to Base Address+3FH, for the specific application.
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Zarlink Semiconductor Inc.
MT93L00A
Data Sheet
System Powerup Reset Held Low Delay 100s Reset High MCLK Active Delay 500s Hardware Software
Reg. Reset
Reset Low Delay 1000 ns Reset High
PWUP to "1" Delay 250s PWUP to "0"
Delay 500s ECAN Ready
Figure 10 - Power Up Sequence Flow Diagram
Power Management
Each group of echo cancellers can be placed in Power Down mode by writing a "0" into the PWUP bit in their respective Main Control Register. When a given group is in Power Down mode, the corresponding PCM data are bypassed from Rin to Rout and from Sin to Sout with two frames delay. Refer to the Main Control Register section for description. The typical power consumption can be calculated with the following equation:
PC = 9 * Nb_of_groups + 3.6, in mW
where 0 Nb_of_groups 16
Call Initialization
To ensure fast initial convergence on a new call, it is important to clear the Adaptive filter. This is done by putting the echo canceller in bypass mode for at least one frame (125 s) and then enabling adaptation.
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Zarlink Semiconductor Inc.
MT93L00A
Interrupts
Data Sheet
The MT93L00 provides an interrupt pin (IRQ) to indicate to the HOST processor when a G.164 or G.165 Tone Disable is detected and released. Although the MT93L00 may be configured to react automatically to tone disable status on any input PCM voice channels, the user may want for the external HOST processor to respond to Tone Disable information in an appropriate, application specific manner. Each echo canceller will generate an interrupt when a Tone Disable occurs and will generate another interrupt when a Tone Disable releases. Upon receiving an IRQ, the HOST CPU should read the Interrupt FIFO Register. This register is a FIFO memory containing the channel number of the echo canceller that has generated the interrupt. All pending interrupts from any of the echo cancellers and their associated input channel number are stored in this FIFO memory. The IRQ always returns high after a read access to the Interrupt FIFO Register. The IRQ pin will toggle low for each pending interrupt. After the HOST CPU has received the channel number of the interrupt source, the corresponding per channel Status Register can be read from internal memory to determine the cause of the interrupt (see Figure 8 for address mapping of Status register). The TD bit indicates the presence of a Tone Disable. The MIRQ bit 5 in the Main Control Register 0 masks interrupts from the MT93L00. To provide more flexibility, the MTDBI (bit 4) and MTDAI (bit 3) bits in the Main Control Register<15:0> allow Tone Disable to be masked or unmasked, from generating an interrupt on a per channel basis. Refer to the Registers Description section.
JTAG Support
The MT93L00 JTAG interface conforms to the Boundary-Scan standard IEEE1149.1. This standard specifies a design-for-testability technique called Boundary-Scan test (BST). The operation of the Boundary Scan circuitry is controlled by an external Test Access Port (TAP) controller. JTAG inputs are 3.3 V compliant only. Test Access Port (TAP) The TAP provides access to many test functions of the MT93L00. It consists of three input pins and one output pin. The following pins are found on the TAP. * Test Clock Input (TCK) The TCK provides the clock for the test logic. The TCK does not interfere with any on-chip clock and thus remains independent. The TCK permits shifting of test data into or out of the Boundary-Scan register cells concurrent with the operation of the device and without interfering with the on-chip logic. Test Mode Select Input (TMS) The logic signals received at the TMS input are interpreted by the TAP Controller to control the test operations. The TMS signals are sampled at the rising edge of the TCK pulse. This pin is internally pulled to VDD1when it is not driven from an external source. Test Data Input (TDI) Serial input data applied to this port is fed either into the instruction register or into a test data register, depending on the sequence previously applied to the TMS input. Both registers are described in a subsequent section. The received input data is sampled at the rising edge of TCK pulses. This pin is internally pulled to VDD1when it is not driven from an external source.
*
*
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Zarlink Semiconductor Inc.
MT93L00A
*
Data Sheet
Test Data Output (TDO) Depending on the sequence previously applied to the TMS input, the contents of either the instruction register or data register are serially shifted out towards the TDO. The data from the TDO is clocked on the falling edge of the TCK pulses. When no data is shifted through the Boundary Scan cells, the TDO driver is set to a high impedance state. Test Reset (TRST) This pin is used to reset the JTAG scan structure. This pin is internally pulled to VSS.
*
Instruction Register In accordance with the IEEE 1149.1 standard, the MT93L00 uses public instructions. The JTAG Interface contains a 3-bit instruction register. Instructions are serially loaded into the instruction register from the TDI when the TAP Controller is in its shifted-IR state. Subsequently, the instructions are decoded to achieve two basic functions: to select the test data register that will operate while the instruction is current, and to define the serial test data register path, which is used to shift data between TDI and TDO during data register scanning. Test Data Registers As specified in IEEE 1149.1, the MT93L00 JTAG Interface contains three test data registers: * Boundary-Scan register The Boundary-Scan register consists of a series of Boundary-Scan cells arranged to form a scan path around the boundary of the MT93L00 core logic. Bypass Register The Bypass register is a single stage shift register that provides a one-bit path from TDI TDO. Device Identification register The Device Identification register provides access to the following encoded information: device version number, part number and manufacturer's name.
* *
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Zarlink Semiconductor Inc.
MT93L00A
Register Descriptions
Echo Canceller A, Control Register A1
Data Sheet
Read/Write Address: 00H + Base Address 0
ExtDl
7
Reset
6
INJDis
5
BBM
4
PAD
3
2
1
0
Bypass AdpDis
Reset Value:
00H.
Echo Canceller B, Control Register B1 7
Reset
Read/Write Address: 20H + Base Address 0
0
6
INJDis
5
BBM
4
PAD
3
2
1
1
Bypass AdpDis
Reset Value:
02H.
Bit 7 6 5
Name Reset INJDis BBM
Description When high, the power-up initialization is executed which presets all register bits including this bit and clears the Adaptive Filter coefficients. When high, the noise injection process is disabled. When low noise injection is enabled. When high the Back to Back configuration is enabled. When low the Normal configuration is enabled. Note: Do not enable Extended-Delay and BBM configurations at the same time. Always set both BBM bits of the two echo cancellers (Control Register A1 and Control Register B1) of the same group to the same logic value to avoid conflict. When high, 12 dB of attenuation is inserted into the Rin to Rout path. When low the Rin to Rout path gain is 0 dB. When high, Sin data is by-passed to Sout and Rin data is by-passed to Rout. The Adaptive Filter coefficients are set to zero and the filter adaptation is stopped. When low, output data on both Sout and Rout is a function of the echo canceller algorithm. When high, echo canceller adaptation is disabled. The MT93L00 cancels echo. When low, the echo canceller dynamically adapts to the echo path characteristics. Bits marked as "1" or "0" are reserved bits and should be written as indicated. When high, Echo Cancellers A and B of the same group are internally cascaded into one 128 ms echo canceller. When low, Echo Cancellers A and B of the same group operate independently. Note: Do not enable both Extended-Delay and BBM configurations at the same time. Control Register B1 bit 0 is a reserved bit and should be written "0".
4 3
PAD Bypass
2 1 0
AdpDis 0 or 1 ExtDl or 0
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Zarlink Semiconductor Inc.
MT93L00A
Echo Canceller A, Control Register A2 Echo Canceller B, Control Register B2 7
TDis
Data Sheet
Read/Write Address: 01H + Base Address Read/Write Address: 21H + Base Address 0
MuteR
6
5
4
3
2
1
PHDis NLPDis AutoTD NBDis HPFDis MuteS
Reset Value: Description
00H.
Bit 7
Name TDis
When high, tone detection is disabled. When low, tone detection is enabled. When both Echo Cancellers A and B TDis bits are high, Tone Disable processors are disabled entirely and are put into power down mode. When high, the tone detectors will trigger upon the presence of a 2100 Hz tone regardless of the presence/absence of periodic phase reversals. When low, the tone detectors will trigger only upon the presence of a 2100 Hz tone with periodic phase reversals. When high, the non-linear processor is disabled. When low, the non-linear processors function normally. Useful for G.165 conformance testing. When high, the echo canceller puts itself in Bypass mode when the tone detectors detect the presence of 2100 Hz tone. See PHDis for qualification of 2100 Hz tones. When low, the echo canceller algorithm will remain operational regardless of the state of the 2100 Hz tone detectors. When high, the narrow-band detector is disabled. When low, the narrow-band detector is enabled. When high, the offset nulling high pass filters are bypassed in the Rin and Sin paths. When low, the offset nulling filters are active and will remove DC offsets on PCM input signals. When high, data on Sout is muted to quiet code. When low, Sout carries active code. When high, data on Rout is muted to quiet code. When low, Rout carries active code.
6
PHDis
5
NLPDis
4
AutoTD
3 2
NBDis HPFDis
1 0
MuteS MuteR
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Zarlink Semiconductor Inc.
MT93L00A
Echo Canceller A, Flat Delay Register (FD) Echo Canceller B, Flat Delay Register (FD) 7
FD7
Data Sheet
Read/Write Address: 04h + Base Address Read/Write Address: 24h + Base Address 2
FD2
6
FD6
5
FD5
4
FD4
3
FD3
1
FD1
0
FD0 Power Reset Value 00h
Echo Canceller A, Decay Step Number Register (NS) Echo Canceller B, Decay Step Number Register (NS) 7
NS7
Read/Write Address: 07h + Base Address Read/Write Address: 27h + Base Address 0
NS0 Power Reset Value 00h
6
NS6
5
NS5
4
NS4
3
NS3
2
NS2
1
NS1
Echo Canceller A, Decay Step Size Control Register (SSC) Echo Canceller B, Decay Step Size Control Register (SSC) 7
0
Read/Write Address: 06h + Base Address Read/Write Address: 26h + Base Address 0
SSC0 Power Reset Value 04h
6
0
5
0
4
0
3
0
2
SSC2
1
SSC1
Note: Bits marked with "0" are reserved bits and should be written "0". Amplitude of MU FIR Filter Length (512 or 1024 taps) 1.0 Step Size (SS) Flat Delay (FD7-0)
2-16
Time Number of Steps (NS7-0)
The Exponential Decay registers (Decay Step Number and Decay Step Size) and Flat Delay register allow the LMS adaptation stepsize (MU) to be programmed over the length of the FIR filter. A programmable MU profile allows the performance of the echo canceller to be optimized for specific applications. For example, if the characteristic of the echo response is known to have a flat delay of several milliseconds and a roughly exponential decay of the echo impulse response, then the MU profile can be programmed to approximate this expected impulse response thereby improving the convergence characteristics of the Adaptive Filter. Note that in the following register descriptions, one tap is equivalent to 125 s (64 ms/512 taps). FD7-0 Flat Delay: This register defines the flat delay of the MU profile, (i.e., where the MU value is 2-16). The delay is defined as FD7-0 x 8 taps. For example; if FD7-0 = 5, then MU=2-16 for the first 40 taps of the echo canceller FIR filter. The valid range of FD 7-0 is: 0 FD7-0 64 in normal mode and 0 FD7-0 128 in extended-delay mode. The default value of FD7-0 is zero.
SSC 2-0 Decay Step Size Control: This register controls the step size (SS) to be used during the exponential decay of MU. The decay rate is defined as a decrease of MU by a factor of 2 every SS taps of the FIR filter, where SS = 4 x2SSC2-0. For example; If SSC2-0 = 4, then MU is reduced by a factor of 2 every 64 taps of the FIR filter. The default value of SSC 2-0 is 04h. NS 7-0 Decay Step Number: This register defines the number of steps to be used for the decay of MU where each step has a period of SS taps (see SSC 2-0). The start of the exponential decay is defined as: Filter Length (512 or 1024) - [Decay Step Number (NS7-0) x Step Size (SS)] where SS = 4 x 2SSC2-0. For example, if NS 7-0=4 and SSC 2-0=4, then the exponential decay start value is 512 - [NS7-0 x SS] = 512 - [4x (4x2 4)] = 256 taps for a filter length of 512 taps.
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Zarlink Semiconductor Inc.
MT93L00A
Echo Canceller A, Status Register Echo Canceller B, Status Register 7
res
Data Sheet
02H + Base Address 22H + Base Address
Read Address: Read Address: 1 0
NB
6
TD
5
DTDet
4
res
3
res
2
res
TDG
Reset Value: Description
00H.
Bit 7 6 5 4 3 2 1
Name res TD DTDet res res res TDG Reserved bit.
Logic high indicates the presence of a 2100 Hz tone. Logic high indicates the presence of a double-talk condition. Reserved bit. Reserved bit. Reserved bit. Tone detection status bit gated with the AutoTD bit. Logic high indicates that AutoTD has been enabled and the tone detector has detected the presence of a 2100 Hz tone. Logic high indicates the presence of a narrow-band signal on Rin.
0
NB
Echo Canceller A, Control Register A3 Echo Canceller B, Control Register B3 7
res
Read/Write Address: 08H + Base Address Read/Write Address: 28H + Base Address 0
res
6
res
5
res
4
res
3
2
1
RingClr PathClr PathDet
Reset Value: Description
0AH.
Bit 7-4 3 2
Name res RingClr PathClr
Reserved bits. Must always be set to zero for normal operation. When high, the instability detector is activated. When low, the instability detector is disabled When high, the current echo channel estimate will be cleared and the echo canceller will enter fast convergence mode upon detection of a path change. When low, the echo canceller will keep the current path estimate but revert to fast convergence mode upon detection of a path change. Note: this bit is ignored if PathDet is low. When high, the path change detector is activated. When low, the path change detector is disabled. Reserved bit. Must always be set to zero for normal operation.
1 0
PathDet res
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Zarlink Semiconductor Inc.
MT93L00A
Echo Canceller A, Control Register A4 Echo Canceller B, Control Register B4 7
0
Data Sheet
Read/Write Address: 09H + Base Address Read/Write Address: 29H + Base Address 0
res
6
SD2
5
SD1
4
SD0
3
res
2
res
1
res
Reset Value: Description
50H.
Bit 7 6-4
Name 0 SupDec Must be set to zero.
These three bits control how long the echo canceller remains in a fast convergence state following a path change, Reset or Bypass operation. A value of zero will keep the echo canceller in fast convergence indefinitely. Reserved bits. Must always be set to zero for normal operation.
3-0
res
Echo Canceller A, Noise Scaling (NS) Echo Canceller B, Noise Scaling (NS) 7
NS7
Read/Write Address: 0Ah + Base Address Read/Write Address: 2Ah + Base Address 2
NS2
6
NS6
5
NS5
4
NS4
3
NS3
1
NS1
0
NS0
Power Reset Value 74h
If the comfort noise level estimator is unable to correctly match the background noise level, this register can be used to scale the comfort noise up or down. A neutral value of 80h will prevent any scaling. Values less than 80h will scale the comfort noise level down. Values greater than 80h will scale the comfort noise level up. Scaling is done linearly, so to scale the comfort noise down by 1 dB, a value of 72h would be used (-1 dB = 89% of original level, 0.89(dec) * 80h = 72h). Similarly, to scale up by 1 dB, use a value of 8Fh (1 dB = 112% of original level, 1.12(dec) * 80h = 8Fh).
Echo Canceller A, Injection Rate (IR) Echo Canceller B, Injection Rate (IR) 7
IR7
Read/Write Address: 0Bh + Base Address Read/Write Address: 2Bh + Base Address 2
IR2
6
IR6
5
IR5
4
IR4
3
IR3
1
IR1
0
IR0
Power Reset Value 0Ch
The NLP ramps-in comfort noise during the initial background noise estimation stage. This register provides control over the ramp-in speed. Higher values will increase the ramp-in speed.
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Zarlink Semiconductor Inc.
MT93L00A
Echo Canceller A, Rin Peak Detect Register 2 (RP) Echo Canceller B, Rin Peak Detect Register 2 (RP) 7
RP15
Data Sheet
Read Address: 0Dh + Base Address Read Address: 2Dh + Base Address
6
RP14
5
RP13
4
RP12
3
RP11
2
RP10
1
RP9
0
RP8
Power Reset Value N/A
Echo Canceller A, Rin Peak Detect Register 1 (RP) Echo Canceller B, Rin Peak Detect Register 1 (RP) 7 6 5 4 3 2 1
RP7 RP6 RP5 RP4 RP3 RP2 RP1
Read Address: 0Ch + Base Address Read Address: 2Ch + Base Address 0
RP0 Power Reset Value N/A
These peak detector registers allow the user to monitor the receive in signal (Rin) peak signal level. The information is in 16 bit 2's complement linear coded format presented in two 8 bit registers for each echo canceller. The high byte is in Register 2 and the low byte is in Register 1.
Echo Canceller A, Sin Peak Detect Register 2 (SP) Echo Canceller B, Sin Peak Detect Register 2 (SP) 7
SP15
Read Address: 0Fh + Base Address Read Address: 2Fh + Base Address 1
SP9
6
SP14
5
SP13
4
SP12
3
SP11
2
SP10
0
SP8
Power Reset Value N/A
Echo Canceller A, Sin Peak Detect Register 1 (SP) Echo Canceller B, Sin Peak Detect Register 1 (SP) 7
SP7
Read Address: 0Eh + Base Address Read Address: 2Eh + Base Address 1 0
SP0 Power Reset Value N/A
6
SP6
5
SP5
4
SP4
3
SP3
2
SP2
SP1
These peak detector registers allow the user to monitor the send in signal (Sin) peak signal level. The information is in 16 bit 2's complement linear coded format presented in two 8 bit registers for each echo canceller. The high byte is in Register 2 and the low byte is in Register 1.
Echo Canceller A, Error Peak Detect Register 2 (EP) Echo Canceller B, Error Peak Detect Register 2 (EP) 7
EP15
Read Address: 11h + Base Address Read Address: 31h + Base Address 0
EP8 Power Reset Value N/A
6
EP14
5
EP13
4
EP12
3
EP11
2
EP10
1
EP9
Echo Canceller A, Error Peak Detect Register 1 (EP) Echo Canceller B, Error Peak Detect Register 1 (EP) 7
EP7
Read Address: 10h + Base Address Read Address: 30h + Base Address 0
EP0 Power Reset Value N/A
6
EP6
5
EP5
4
EP4
3
EP3
2
EP2
1
EP1
These peak detector registers allow the user to monitor the error signal peak level. The information is in 16 bit 2's complement linear coded format presented in two 8 bit registers for each echo canceller. The high byte is in Register 2 and the low byte is in Register 1.
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Zarlink Semiconductor Inc.
MT93L00A
Data Sheet
Echo Canceller A, Double-Talk Detection Threshold Register 2 Read/Write Address: 15h + Base Address Echo Canceller B, Double-Talk Detection Threshold Register 2 Read/Write Address: 35h + Base Address 7
DTDT15
6
DTDT14
5
DTDT13
4
DTDT12
3
DTDT11
2
DTDT10
1
DTDT9
0
DTDT8
Power Reset Value 48h
(DTDT)
Echo Canceller A, Double-Talk Detection Threshold Register 1 Read/Write Address: 14h + Base Address Echo Canceller B, Double-Talk Detection Threshold Register 1 Read/Write Address: 34h + Base Address 7 6 5 4 3 2 1 0 Power Reset Value
DTDT7 DTDT6 DTDT5 DTDT4 DTDT3 DTDT2 DTDT1 DTDT0
(DTDT)
00h
This register allows the user to program the level of Double-Talk Detection Threshold (DTDT). The 16 bit 2's complement linear value defaults to 4800h= 0.5625 or -5 dB. The maximum value is 7FFFh = 0.9999 or 0 dB. The high byte is in Register 2 and the low byte is in Register 1.
Echo Canceller A, Non-Linear Processor Threshold Register 2 Read/Write Address: 19h + Base Address Echo Canceller B, Non-Linear Processor Threshold Register 2 Read/Write Address: 39h + Base Address 7
NLP15
6
NLP14
5
NLP13
4
NLP12
3
NLP11
2
NLP10
1
NLP9
0
NLP8
Power Reset Value 0Bh
(NLPTHR)
Echo Canceller A, Non-Linear Processor Threshold Register 1 Read/Write Address: 18h + Base Address Echo Canceller B, Non-Linear Processor Threshold Register 1 Read/Write Address: 38h + Base Address 7 6 5 4 3 2 1 0
NLP7 NLP6 NLP5 NLP4 NLP3 NLP2 NLP1 NLP0
(NLPTHR)
Power Reset Value 60h
This register allows the user to program the level of the Non-Linear Processor Threshold (NLPTHR). The 16 bit 2's complement linear value defaults to 0B60h = 0.0889 or -21.0 dB. The maximum value is 7FFFh = 0.9999 or 0 dB. The high byte is in Register 2 and the low byte is in Register 1.
Echo Canceller A, Adaptation Step Size (MU) Register 2 Echo Canceller B, Adaptation Step Size (MU) Register 2 7
MU15
Read/Write Address: 1Bh + Base Address Read/Write Address: 3Bh + Base Address 0
MU8 Power Reset Value 40h
6
MU14
5
MU13
4
MU12
3
MU11
2
MU10
1
MU9
(MU)
Read/Write Address: 1Ah + Base Address Read/Write Address: 3Ah + Base Address
Echo Canceller A, Adaptation Step Size (MU) Register 1 Echo Canceller B, Adaptation Step Size (MU) Register 1 7 6 5 4 3 2 1
MU7 MU6 MU5 MU4 MU3 MU2 MU1
0
MU0
(MU)
Power Reset Value 00h
This register allows the user to program the level of MU. MU is a 16 bit 2's complement value which defaults to 4000h = 1.0 The maximum value is 7FFFh or 1.9999 decimal. The high byte is in Register 2 and the low byte is in Register 1.
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Zarlink Semiconductor Inc.
MT93L00A
Main Control Register 0 7
WR_all
Data Sheet
(EC group 0) 2 1
LAW
Read/Write Address: 400H 0
PWUP
6
ODE
5
MIRQ
4
MTDBI
3
MTDAI Format
Reset Value:
00H.
Bit 7
Name WR_all
Description Write all control bit: When high, Group 0-15 Echo Cancellers Registers are mapped into 0000h to 0003Fh which is Group 0 address mapping. Useful to initialize the 16 Groups of Echo Cancellers as per Group 0. When low, address mapping is per Figure 9. Note: Only the Main Control Register 0 has the WR_all bit. Output Data Enable: This control bit is logically AND'd with the ODE input pin. When both ODE bit and ODE input pin are high, the Rout and Sout outputs are enabled. When the ODE bit is low or the ODE input pin is low, the Rout and Sout outputs are high impedance. Note: Only the Main Control Register 0 has the ODE bit. Mask Interrupt: When high, all the interrupts from the Tone Detectors output are masked. The Tone Detectors operate as specified in their Echo Canceller B, Control Register 2. When low, the Tone Detectors Interrupts are active. Note: Only the Main Control Register 0 has the MIRQ bit. Mask Tone Detector B Interrupt: When high, the Tone Detector interrupt output from Echo Canceller B is masked. The Tone Detector operates as specified in Echo Canceller B, Control Register 2. When low, the Tone Detector B Interrupt is active. Mask Tone Detector A Interrupt: When high, the Tone Detector interrupt output from Echo Canceller A is masked. The Tone Detector operates as specified in Echo Canceller A, Control Register 2. When low, the Tone Detector A Interrupt is active. ITU-T/Sign Mag: When high, both Echo Cancellers A and B for a given group, accept ITU-T (G.711) PCM code. When low, both Echo Cancellers A and B for a given group, accept sign-magnitude PCM code. A/ Law: When high, both Echo Cancellers A and B for a given group, accept A-Law companded PCM code. When low, both Echo Cancellers A and B for a given group, accept -Law companded PCM code.
6
ODE
5
MIRQ
4
MTDBI
3
MTDAI
2
Format
1
LAW
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Zarlink Semiconductor Inc.
MT93L00A
Main Control Register 0 7
WR_all
Data Sheet
(EC group 0) 2 1
LAW
Read/Write Address: 400H 0
PWUP
6
ODE
5
MIRQ
4
MTDBI
3
MTDAI Format
Reset Value:
00H.
Bit 0
Name PWUP
Description Power-UP: When high, both Echo Cancellers A and B and Tone Detectors for a given group, are active. When low, both Echo Cancellers A and B and Tone Detectors for a given group, are placed in Power Down mode. In this mode, the corresponding PCM data are bypassed from Rin to Rout and from Sin to Sout with two frames delay. When the PWUP bit toggles from zero to one, the echo canceller A and B execute their initialization routine which presets their registers, Base Address+00H to Base Address+3FH, to default Reset Value and clears the Adaptive Filter coefficients. Two frames are necessary for the initialization routine to execute properly. Once the initialization routine is executed, the user can set the per channel Control Registers for their specific application.
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Zarlink Semiconductor Inc.
MT93L00A
Data Sheet
Main Control Register 1 Main Control Register 2 Main Control Register 3 Main Control Register 4 Main Control Register 5 Main Control Register 6 Main Control Register 7 Main Control Register 8 Main Control Register 9 Main Control Register 10 Main Control Register 11 Main Control Register 12 Main Control Register 13 Main Control Register 14 Main Control Register 15 7 6 5 4 3
(EC group 1) (EC group 2) (EC group 3) (EC group 4) (EC group 5) (EC group 6) (EC group 7) (EC group 8) (EC group 9) (EC group 10) (EC group 11) (EC group 12) (EC group 13) (EC group 14) (EC group 15) 2 1
LAW
Read/Write Address: Read/Write Address: Read/Write Address: Read/Write Address: Read/Write Address: Read/Write Address: Read/Write Address: Read/Write Address: Read/Write Address: Read/Write Address: Read/Write Address: Read/Write Address: Read/Write Address: Read/Write Address: Read/Write Address:
401H 402H 403H 404H 405H 406H 407H 408H 409H 40AH 40BH 40CH 40DH 40EH 40FH
0
PWUP
unused unused unused MTDBI
MTDAI Format
Reset Value:
00H.
Bit 7-5 4
Name unused MTDBI Unused Bits.
Description
Mask Tone Detector B Interrupt: When high, the Tone Detector interrupt output from Echo Canceller B is masked. The Tone Detector operates as specified in Echo Canceller B, Control Register 2. When low, the Tone Detector B Interrupt is active. Mask Tone Detector A Interrupt: When high, the Tone Detector interrupt output from Echo Canceller A is masked. The Tone Detector operates as specified in Echo Canceller A, Control Register 2. When low, the Tone Detector A Interrupt is active. ITU-T/Sign Mag: When high, both Echo Cancellers A and B for a given group, select ITU-T (G.711) PCM code. When low, both Echo Cancellers A and B for a given group, select sign-magnitude PCM code. A/ Law: When high, both Echo Cancellers A and B for a given group, select A-Law companded PCM code. When low, both Echo Cancellers A and B for a given group, select m-Law companded PCM code.
3
MTDAI
2
Format
1
LAW
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Zarlink Semiconductor Inc.
MT93L00A
Data Sheet
Main Control Register 1 Main Control Register 2 Main Control Register 3 Main Control Register 4 Main Control Register 5 Main Control Register 6 Main Control Register 7 Main Control Register 8 Main Control Register 9 Main Control Register 10 Main Control Register 11 Main Control Register 12 Main Control Register 13 Main Control Register 14 Main Control Register 15 7 6 5 4 3
(EC group 1) (EC group 2) (EC group 3) (EC group 4) (EC group 5) (EC group 6) (EC group 7) (EC group 8) (EC group 9) (EC group 10) (EC group 11) (EC group 12) (EC group 13) (EC group 14) (EC group 15) 2 1
LAW
Read/Write Address: Read/Write Address: Read/Write Address: Read/Write Address: Read/Write Address: Read/Write Address: Read/Write Address: Read/Write Address: Read/Write Address: Read/Write Address: Read/Write Address: Read/Write Address: Read/Write Address: Read/Write Address: Read/Write Address:
401H 402H 403H 404H 405H 406H 407H 408H 409H 40AH 40BH 40CH 40DH 40EH 40FH
0
PWUP
unused unused unused MTDBI
MTDAI Format
Reset Value:
00H.
Bit 0
Name PWUP
Description Power-UP: When high, both Echo Cancellers A and B and Tone Detectors for a given group, are active. When low, both Echo Cancellers A and B and Tone Detectors for a given group, are placed in Power Down mode. In this mode, the corresponding PCM data are bypassed from Rin to Rout and from Sin to Sout with two frames delay. When the PWUP bit toggles from zero to one, the echo cancellers A and B execute their initialization routine which presets their registers, Base Address+00H to Base Address+3FH, to default Reset Value and clears the Adaptive Filter coefficients. Two frames are necessary for the initialization routine to execute properly. Once the initialization routine is executed, the user can set the per channel Control Registers for their specific application.
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Zarlink Semiconductor Inc.
MT93L00A
Data Sheet
Interrupt FIFO Register
Read Address:
410H (Read only)
7
IRQ
6
0
5
0
4
I4
3
I3
2
I2
1
I1
0
I0
Reset Value: Description
00H.
Bit 7
Name IRQ
Logic high indicates an interrupt has occurred. IRQ bit is cleared after the Interrupt FIFO register is read. Logic Low indicates that no interrupt is pending and the FIFO is empty. Unused bits. Always zero I<4:0> binary code indicates the channel number at which a Tone Detector state change has occurred. Note: Whenever a Tone Disable is detected or released, an interrupt is generated.
6:5 4:0
0 I<4:0>
Test Register
Read/Write Address: 411H
7
res
6
res
5
res
4
res
3
res
2
res
1
res
0
Tirq
Reset Value: Description
00H.
Bit 7:1 0
Name res Tirq
Reserved bits. Must always be set to zero for normal operation. Test IRQ: Useful for the application engineer to verify the interrupt service routine. When high, any change to MTDBI and MTDAI bits of the Main Control Register will cause an interrupt and its corresponding channel number will be available from the Interrupt FIFO Register. When low, normal operation is selected.
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Zarlink Semiconductor Inc.
MT93L00A
Absolute Maximum Ratings*
Parameter 1 2 3 4 5 6 I/O Supply Voltage (VDD1) Core Supply Voltage (VDD2) Input Voltage Input Voltage on any 5 V Tolerant I/O pins Continuous Current at digital outputs Package power dissipation Symbol VDD_IO VDD_CORE VI3 VI5 Io PD Min. -0.5 -0.5 VSS - 0.5 VSS - 0.3 Max. 5.0 2.5
Data Sheet
Units V V V V mA W C
VDD1+0.5 7.0 20 2 150
-55 7 Storage temperature TS * Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
Recommended Operating Conditions - Voltages are with respect to ground (Vss) unless otherwise stated.
Characteristics 1 2 3 4 5 6 Operating Temperature I/O Supply Voltage (VDD_IO) Core Supply Voltage (VDD_CORE) Input High Voltage on 3.3 V tolerant I/O Input High Voltage on 5 V tolerant I/O pins Input Low Voltage Sym. TOP VDD1 VDD2 VIH3 VIH5 VIL Min. -40 3.0 1.7 0.7VDD1 0.7VDD1 3.3 1.8 Typ. Max. +85 3.6 1.9 VDD1 5.5 0.3VDD1 Units C V V V V V
Typical figures are at 25C and are for design aid only: not guaranteed and not subject to production testing.
DC Electrical Characteristics - Voltages are with respect to ground (Vss) unless otherwise stated.
Characteristics Static Supply Current 1 IDD_IO (VDD1 = 3.3 V) IDD_CORE (VDD2 = 1.8 V) 2 3 4 5
I N P U T S
Sym. ICC IDD_IO IDD_CORE PC VIH VIL IIH/IIL ILU ILD CI VOH VOL IOZ CO
Min.
Typ. 10 65 150
Max. 250
Units A mA mA mW V
Test Conditions RESET = 0 All 32 channels active All 32 channels active All 32 channels active
Power Consumption Input High Voltage Input Low Voltage Input Leakage Input Leakage on Pullup Input Leakage on Pulldown Input Pin Capacitance
0.7VDD1 0.3VDD1 -30 30 10 -55 65 10 0.8VDD1 0.4 10 10
V A A A pF V V A pF IOH = 12 mA IOL = 12 mA VIN=VSS to 5.5 V VIN=VSS to VDD1or 5.5 V VIN=VSS VIN=VDD1 See Note 1
6 7 8 9 10
O U T P U T S
Output High Voltage Output Low Voltage High Impedance Leakage Output Pin Capacitance
Characteristics are over recommended operating conditions unless otherwise stated. Typical figures are at 25C, VDD1 =3.3 V and are for design aid only: not guaranteed and not subject to production testing. * Note 1: Maximum leakage on pins (output or I/O pins in high impedance state) is over an applied voltage (VIN).
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Zarlink Semiconductor Inc.
MT93L00A
Data Sheet
AC Electrical Characteristics - Timing Parameter Measurement Voltage Levels
- Voltages are with respect to ground (Vss) unless otherwise stated.
Characteristics 1 2 CMOS Threshold CMOS Rise/Fall Threshold Voltage High
Sym. VTT VHM
Level 0.5VDD1 0.7VDD1
Units V V V
Conditions
3 CMOS Rise/Fall Threshold Voltage Low VLM 0.3VDD1 Characteristics are over recommended operating conditions unless otherwise stated.
i
AC Electrical Characteristics - Frame Pulse and C4i
Characteristic 1 Frame pulse width (ST-BUS, GCI) 2 Frame Pulse Setup time before C4i falling (ST-BUS or GCI) 3 Frame Pulse Hold Time from C4i falling (ST-BUS or GCI) 4 C4i Period 5 C4i Pulse Width High 6 C4i Pulse Width Low 7 C4i Rise/Fall Time Sym.
tFPW tFPS tFPH tCP tCH tCL tr, tf
Min. 20 10 10 190 85 85
Typ.
Max. 2*
tCP-20
Units ns ns ns ns ns ns ns
Notes
122 122 244.1
150 150 300 150 150 10
Characteristics are over recommended operating conditions unless otherwise stated. Typical figures are at 25C, VDD1 = 3.3 V and for design aid only: not guaranteed and not subject to production testing.
AC Electrical Characteristics - Serial Streams for ST-BUS and GCI Backplanes
Characteristic 1 2 3 4 Rin/Sin Set-up Time Rin/Sin Hold Time Rout/Sout Delay - Active to Active Output Data Enable (ODE) Delay Sym.
tSIS tSIH tSOD
Min. 10 10
Typ.
Max.
Units ns ns
Test Conditions
60 30
ns ns
CL=150 pF CL=150 pF, RL=1 K See Note 1
tODE
Characteristics are over recommended operating conditions unless otherwise stated. Typical figures are at 25C, VDD1 = 3.3 V and for design aid only: not guaranteed and not subject to production testing. * Note1: High Impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel time taken to discharge CL.
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Zarlink Semiconductor Inc.
MT93L00A
Data Sheet
tFPW F0i tFPS C4i tSOD Rout/Sout
Bit 0, Channel 31 Bit 7, Channel 0 Bit 6, Channel 0 Bit 5, Channel 0
VTT tFPH tCP tCH tCL tr VHM VTT VLM tf VTT
tSIS Rin/Sin
Bit 0, Channel 31
tSIH
Bit 6, Channel 0 Bit 5, Channel 0
Bit 7, Channel 0
VTT
Figure 11 - ST-BUS Timing at 2.048 Mbps
tFPW F0i tFPS C4i tSOD Sout/Rout
Bit 7, Channel 31) Bit 0, Channel 0 Bit 1, Channel 0 Bit 2, Channel 0
VTT tFPH tCP tCH tCL tr VHM VTT VLM tf VTT
tSIS Sin/Rin
Bit 7, Channel 31)
tSIH
Bit 1, Channel 0 Bit 2, Channel 0
Bit 0, Channel 0
VTT
Figure 12 - GCI Interface Timing at 2.048 Mbps
ODE tODE Sout/Rout HiZ tODE
VTT
Valid Data
HiZ
VTT
Figure 13 - Output Driver Enable (ODE)
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Zarlink Semiconductor Inc.
MT93L00A
Data Sheet
AC Electrical Characteristics - Master Clock - Voltages are with respect to ground (VSS). unless otherwise stated.
Characteristic 1 Master Clock Frequency, - Fsel = 0 - Fsel = 1 2 Master Clock Low 3 Master Clock High Sym.
fMCF0 fMCF1 tMCL tMCH
Min. 19.0 9.5 20 20
Typ. 20.0 10.0
Max. 21.0 10.5
Units MHz MHz ns ns
Notes
Characteristics are over recommended operating conditions unless otherwise stated. Typical figures are at 25C, VDD1 = 3.3 V and for design aid only: not guaranteed and not subject to production testing.
tMCH
MCLK
VTT
tMCL
Figure 14 - Master Clock
AC Electrical Characteristics - Motorola Non-Multiplexed Bus Mode
Characteristics 1 2 3 4 5 6 7 8 9 CS setup from DS falling R/W setup from DS falling Address setup from DS falling CS hold after DS rising R/W hold after DS rising Address hold after DS rising Data delay on read Data hold on read Data setup on write Sym. tCSS tRWS tADS tCSH tRWH tADH tDDR tDHR tDSW tDHW tAKD tAKH tIRD 0 20 3 0 0 80 8 65 Min. 0 0 0 0 0 0 79 15 Typ. Max. Units ns ns ns ns ns ns ns ns ns ns ns ns ns CL=150 pF, RL=1 K CL=150 pF, RL=1 K, See Note 1 CL=150 pF, RL=1 K, See Note 1 CL=150 pF, RL=1 K CL=150 pF, RL=1 K See Note 1 Test Conditions
10 Data hold on write 11 Acknowledgment delay 12 Acknowledgment hold time 13 IRQ delay
Characteristics are over recommended operating conditions unless otherwise stated. Typical figures are at 25C, VDD1 = 3.3 V and for design aid only: not guaranteed and not subject to production testing. * Note 1: High Impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel time taken to discharge CL.
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Zarlink Semiconductor Inc.
MT93L00A
Data Sheet
DS
tCSS
tCSH
VTT VTT
CS tRWS R/W tADS A0-A10
VALID ADDRESS
tRWH VTT tADH VTT tDHR
VALID READ DATA
tDDR D0-D7 READ D0-D7 WRITE
VTT
tDSW
VALID WRITE DATA
tDHW VTT tAKH VTT tIRD
tAKD DTA
IRQ
VTT
Figure 15 - Motorola Non-Multiplexed Bus Timing
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Zarlink Semiconductor Inc.
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